How an AI Chip Is Made: From Design to Fab to Data Center

An AI chip is not made by one company in one factory. A design firm such as Nvidia draws up the processor. A contract manufacturer such as TSMC builds it on silicon wafers. Memory makers supply stacked memory, and a packaging step joins the pieces. Contract assemblers test the result and build it into servers.

Nvidia says in its annual report that it relies on outside suppliers for every phase of manufacturing. It also says it has experienced lead times of more than 12 months.

The main stages, in order:

1. Design by a chip company that owns no factories
2. Wafer fabrication at a foundry
3. Memory production, mainly high-bandwidth memory (HBM)
4. Advanced packaging that joins processor and memory
5. Testing, system assembly and delivery to a data center

Who designs AI chips, and who manufactures them?

Many AI chip designers are fabless. That means they design chips but do not own fabrication plants. ASML, the Dutch maker of chipmaking machines, lists:

• Nvidia, AMD and Qualcomm as fabless companies
• TSMC, GlobalFoundries and UMC as foundries that manufacture under contract
• Intel and Samsung as integrated manufacturers that do both

Nvidia's filing for the fiscal year that ended January 25, 2026 shows where its effort goes. About 31,000 of its roughly 42,000 employees worked in research and development. The filing names TSMC and Samsung among the foundries that produce its wafers.

Manufacturing is concentrated. TrendForce, a market research firm, estimated that TSMC held 72.5 percent of the foundry market by revenue in the second quarter of 2026.

How is a chip made inside a fab?

A fab, short for fabrication plant, builds chips layer by layer on thin discs of silicon called wafers. They are most often 300 millimeters across. ASML describes a repeating cycle:

1. A thin film of material is deposited on the wafer.
2. It is coated with a light-sensitive chemical called photoresist.
3. It is exposed to patterned light in a lithography machine.
4. It is etched to reveal the pattern.
5. It is implanted with ions to control how electricity flows.

ASML says the full process takes hundreds of steps or more. It also says a modern chip can have up to 100 layers.

The work happens in cleanrooms. ASML says they are about 10,000 times cleaner than outside air. The reason is that a speck of dust can ruin a chip.

The finest details are printed with extreme ultraviolet (EUV) lithography. It uses light at a wavelength of 13.5 nanometers. ASML says the technology is unique to the company. Its machines make that light by firing laser pulses at droplets of tin, up to 50,000 times per second.

Names such as 3-nanometer and 2-nanometer label successive generations of manufacturing technology. TSMC says its 2-nanometer process, called N2, entered volume production in the fourth quarter of 2025. It says the process uses a new transistor design known as nanosheet.

In its second-quarter 2026 results, TSMC said 5-nanometer chips accounted for 33 percent of wafer revenue. It said 3-nanometer chips accounted for 30 percent and 2-nanometer chips for 3 percent.

What are HBM and CoWoS packaging?

A finished wafer is cut into individual chips, called dies. An AI accelerator also needs fast memory right beside the processor die.

That memory is HBM. Micron describes it as multiple DRAM memory dies stacked vertically and linked by thousands of microscopic vertical connections. The stack is then mounted alongside the processor on a silicon base layer called an interposer, Micron says. Nvidia says it buys memory from SK hynix, Micron and Samsung.

Joining these parts is the job of advanced packaging. TSMC's technology is called CoWoS, short for chip-on-wafer-on-substrate. The company describes it as a platform that integrates processor chips with HBM stacks on an interposer. Nvidia's Blackwell data center chips combine two large processor dies with eight HBM stacks using CoWoS, according to The Register.

Where does an AI chip go after packaging?

Nvidia says contract manufacturers including Hon Hai Precision Industry, Wistron and Fabrinet assemble, test and package its final products. For data center customers, the product can be a complete rack of equipment rather than a single chip. In August 2026, Nvidia said racks of its Vera Rubin platform were running at partners including CoreWeave, Google Cloud, Microsoft Azure and Oracle.

The route can involve more than one country. In October 2025, Nvidia marked the first Blackwell wafer from TSMC's Arizona plant. The Register reported then that such wafers would likely still go to Taiwan for packaging. It said that was because all of TSMC's packaging plants were located there at the time.

What to watch

Packaging and leading-edge capacity outside Taiwan are one thing to track. As of October 2026, TSMC says it began the initial stages of construction on its first Arizona advanced packaging plant in early 2026. It also says it is targeting the second half of 2027 for volume production on its 3-nanometer (N3) process at its second Arizona fab.

Competition is the other. The Register reported in February 2026 that Samsung had begun 2-nanometer volume production in late 2025. It also reported that Rapidus was aiming for mass production at that node by 2027. Rapidus is a Japanese chipmaker funded partly by the Japanese government. Whether either can win large AI chip orders from TSMC is an open question.